Internal logic circuits on a large scale integrated circuit chip characteristically have a relatively low output capacitance and are generally incapable of driving the large capacitive loads presented by a normal I/O pad and testing instrumentation. For example, FIG. 1 illustrates a prior art attempt at a direct connection of a probe having a characteristic capacitance to ground C.sub.t of approximately 20 pf when in contact with a conventional metal I/O pad having a dimension of approximately 100 microns by 100 microns on a side. The capacitance to ground of such a pad would be approximately 0.5 pf. An internal circuit such as a NAND, NOR or other logic function is normally connected to an output line having a characteristic capacitance to ground C.sub.L of approximately 0.5 pf. As is seen in FIG. 1, if the internal logic circuit attempts to drive the combination of the output line capacitance C.sub.L, the conventional pad capacitance C.sub.p and the probe capacitance C.sub.t, the total capacitance which must be driven by the internal circuit is greater than 20 pf. Since this total capacitance far exceeds the normal load capacitance for which an internal circuit is designed in its normal operating environment, the rise time and delay times for signals output by the internal circuit under test are extremely distorted.
Another approach in the prior art to solving this testing problem is the inclusion of an off chip driver (OCD) circuit between the internal logic circuit and the output pad. However, for testing the rise time or delay times of signals from the internal logic circuit, an OCD circuit confuses the measurement since an OCD typically has greater than three times the time delay of an internal logic circuit. This approach obliterates the rise time and fall time of the internal logic circuit.